In semiconductor manufacturing, semiconductor wafers often undergo many processing steps or stages before a completed die is formed. For example, such processing steps may include lithography, etching, semiconductor doping, and deposition of various materials on the semiconductor wafer. Accuracy and precision of the processing, as well as transitions between different processing steps, often directly impacts the quality of the completed die. For example, misalignment of a gate structure, imprecise doping concentrations, or dielectric layers that are too thick or thin may cause an undesirable amount of leakage current in a transistor or delay in the operation of the circuit.
Further complicating this problem may be a semiconductor manufacturer's desire to maximize the number of dies produced by the processing steps. In an attempt to maximize productivity, a manufacturer may provide many tools for each processing step. However, each tool may have a behavior different from other tools within the particular processing step. Accordingly, determining abnormal tool and stage behavior between different tools in different steps may be difficult.
Conventional methods attempt to diagnose tool and processing stage behavior have existed in one dimension, wherein an analysis of variance (ANOVA) is used to rank suspect tools and/or processing stages. Another one-dimensional diagnosis utilizes a correlation coefficient in order to screen wafer acceptance testing (WAT) or in-line measurements. Such techniques would then be utilized to generate a scatter plot, wherein abnormal tools or stages are manually determined by eye.